Response: Intel: High Quality Built-in PHYs Simplify ToR Switch Designs

In this blog post, I believe that Intel is talking about their merchant silicon for Ethernet switches (previously Fulcrum) and the fact that the next generation of chips will have the PHY silicon integrated into the core chip:


At Intel, we took a different approach. With the knowledge that many of our customers are designing low-latency ToR switches using DA copper cabling, we chose to embed high quality 10G PHYs within our Intel Ethernet FM6000 series switch silicon. These PHYs can drive up to 7m of SFP+ DA copper on 10GbE ports or up to 5m of QSFP DA copper on 40GbE ports. With up to 72 10G SerDes on the FM6000, this eliminates up to 18 external quad PHY chips that must be used when lower quality SerDes are used within the switch ASIC. Elimination of these external PHYs saves cost, power and board area, which are critical in today’s large, flat data center installations.

Today, a switch contains the core silicon and several support chips that provide the PHY for the Ethernet ports. PHY density varies according to actual silicon used. For example, this is a silicon architecture for a Cisco C3750/C3560 switch [1]

As you can see there is a PHY chip that has eight Ethernet ports.

Less chips on the board means less cost to design, manufacture and maintain. This should mean cheaper pricing on switches made with these future chips.

The EtherealMind View

The world isn’t going to change overnight because of this. However, where scarcity of silicon once protected network vendors from competition, this is a another disruption in the business model. Cisco says it will continue to develop and support it’s own chips, as does Brocade. Arista is completely promiscuous about it’s use of other people’s silicon. At the least, you can use the 80/20 rule, 80% of the functionality can be provided with 20% of the effort using merchant silicon.

Now, do you need, and want to pay for, the other 20% ?


I have nothing to disclose in this article. My full disclosure statement is here

via High Quality Built-in PHYs Simplify ToR Switch Designs.

Taken from BRKARC-3437 Cisco Catalyst 3750/3560 and 2960 Series Switching Architecture – Cisco Live 2012 ↩

About Greg Ferro

Greg Ferro is a Network Engineer/Architect, mostly focussed on Data Centre, Security Infrastructure, and recently Virtualization. He has over 20 years in IT, in wide range of employers working as a freelance consultant including Finance, Service Providers and Online Companies. He is CCIE#6920 and has a few ideas about the world, but not enough to really count.

He is a host on the Packet Pushers Podcast, blogger at and on Twitter @etherealmind and Google Plus

You can contact Greg via the site contact page.

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